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<div class="header">
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<a href="#pub-methods">Public Member Functions</a> &#124;
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<div class="title">SystemSharp.Components.Std.ROMContractClass Class Reference</div>  </div>
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Inheritance diagram for SystemSharp.Components.Std.ROMContractClass:</div>
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  <map id="SystemSharp.Components.Std.ROMContractClass_map" name="SystemSharp.Components.Std.ROMContractClass_map">
<area href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html" title="Generic register transfer level interface for read-only memory " alt="SystemSharp.Components.Std.IROM" shape="rect" coords="0,0,293,24"/>
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<table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="pub-methods"></a>
Public Member Functions</h2></td></tr>
<tr class="memitem:aedf8ae4d903829f56bee37cf54c055fe"><td class="memItemLeft" align="right" valign="top">void&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m_contract_class.html#aedf8ae4d903829f56bee37cf54c055fe">PreWrite</a> (<a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a> addr, <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a> data)</td></tr>
<tr class="memdesc:aedf8ae4d903829f56bee37cf54c055fe"><td class="mdescLeft">&#160;</td><td class="mdescRight">Pre-initializes the <a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m.html" title="A simple ROM implementation which supports simulation and synthesizable HDL generation. ">ROM</a> with word <em>data</em>  at address <em>addr</em> . Called during elaboration, never at model runtime.  <a href="#aedf8ae4d903829f56bee37cf54c055fe">More...</a><br/></td></tr>
<tr class="separator:aedf8ae4d903829f56bee37cf54c055fe"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table><table class="memberdecls">
<tr class="heading"><td colspan="2"><h2 class="groupheader"><a name="properties"></a>
Properties</h2></td></tr>
<tr class="memitem:a04b44ca23325046e7af84ad36f2929b4"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328eaefeb369cccbd560588a756610865664c">In</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic.html">StdLogic</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m_contract_class.html#a04b44ca23325046e7af84ad36f2929b4">Clk</a><code> [get, set]</code></td></tr>
<tr class="separator:a04b44ca23325046e7af84ad36f2929b4"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:afd294c0cb451b1cf0e9890700fe4b842"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328eaefeb369cccbd560588a756610865664c">In</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m_contract_class.html#afd294c0cb451b1cf0e9890700fe4b842">Addr</a><code> [get, set]</code></td></tr>
<tr class="separator:afd294c0cb451b1cf0e9890700fe4b842"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a48729bef7bb9ba408cc391c245f682ac"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328eaefeb369cccbd560588a756610865664c">In</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic.html">StdLogic</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m_contract_class.html#a48729bef7bb9ba408cc391c245f682ac">RdEn</a><code> [get, set]</code></td></tr>
<tr class="separator:a48729bef7bb9ba408cc391c245f682ac"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ad2919d4ceccfba81e2abfcff6219eb76"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328ea7c147cda9e49590f6abe83d118b7353b">Out</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m_contract_class.html#ad2919d4ceccfba81e2abfcff6219eb76">DataOut</a><code> [get, set]</code></td></tr>
<tr class="separator:ad2919d4ceccfba81e2abfcff6219eb76"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a7272f752627800de2dc8eb9ec5b21751"><td class="memItemLeft" align="right" valign="top">uint&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m_contract_class.html#a7272f752627800de2dc8eb9ec5b21751">Depth</a><code> [get]</code></td></tr>
<tr class="separator:a7272f752627800de2dc8eb9ec5b21751"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0bfb8960b6d0b4a1163a15c861613b2d"><td class="memItemLeft" align="right" valign="top">uint&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m_contract_class.html#a0bfb8960b6d0b4a1163a15c861613b2d">Width</a><code> [get]</code></td></tr>
<tr class="separator:a0bfb8960b6d0b4a1163a15c861613b2d"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="inherit_header properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td colspan="2" onclick="javascript:toggleInherit('properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m')"><img src="closed.png" alt="-"/>&#160;Properties inherited from <a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html">SystemSharp.Components.Std.IROM</a></td></tr>
<tr class="memitem:a6367c7e4cf6b45f5bd23f3ef4cbc4870 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328eaefeb369cccbd560588a756610865664c">In</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic.html">StdLogic</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html#a6367c7e4cf6b45f5bd23f3ef4cbc4870">Clk</a><code> [get, set]</code></td></tr>
<tr class="memdesc:a6367c7e4cf6b45f5bd23f3ef4cbc4870 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="mdescLeft">&#160;</td><td class="mdescRight"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_clock.html" title="A standard clock driver implementation which supports simulation and generation of simulative HDL for...">Clock</a> signal input  <a href="#a6367c7e4cf6b45f5bd23f3ef4cbc4870">More...</a><br/></td></tr>
<tr class="separator:a6367c7e4cf6b45f5bd23f3ef4cbc4870 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:ae0d46f5d122d0058fc19f6427b518caa inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328eaefeb369cccbd560588a756610865664c">In</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html#ae0d46f5d122d0058fc19f6427b518caa">Addr</a><code> [get, set]</code></td></tr>
<tr class="memdesc:ae0d46f5d122d0058fc19f6427b518caa inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="mdescLeft">&#160;</td><td class="mdescRight">Address input  <a href="#ae0d46f5d122d0058fc19f6427b518caa">More...</a><br/></td></tr>
<tr class="separator:ae0d46f5d122d0058fc19f6427b518caa inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a0916ce57e95fe2caa0e2b6bbfe8037a5 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328eaefeb369cccbd560588a756610865664c">In</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic.html">StdLogic</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html#a0916ce57e95fe2caa0e2b6bbfe8037a5">RdEn</a><code> [get, set]</code></td></tr>
<tr class="memdesc:a0916ce57e95fe2caa0e2b6bbfe8037a5 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="mdescLeft">&#160;</td><td class="mdescRight">Read enable  <a href="#a0916ce57e95fe2caa0e2b6bbfe8037a5">More...</a><br/></td></tr>
<tr class="separator:a0916ce57e95fe2caa0e2b6bbfe8037a5 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a9e1a269812f3d87795da339364af2721 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memItemLeft" align="right" valign="top"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328ea7c147cda9e49590f6abe83d118b7353b">Out</a>&lt; <a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a> &gt;&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html#a9e1a269812f3d87795da339364af2721">DataOut</a><code> [get, set]</code></td></tr>
<tr class="memdesc:a9e1a269812f3d87795da339364af2721 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="mdescLeft">&#160;</td><td class="mdescRight">Data output  <a href="#a9e1a269812f3d87795da339364af2721">More...</a><br/></td></tr>
<tr class="separator:a9e1a269812f3d87795da339364af2721 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a614f68bf16763fbfa0fa91d5c9c9e228 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memItemLeft" align="right" valign="top">uint&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html#a614f68bf16763fbfa0fa91d5c9c9e228">Depth</a><code> [get]</code></td></tr>
<tr class="memdesc:a614f68bf16763fbfa0fa91d5c9c9e228 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="mdescLeft">&#160;</td><td class="mdescRight"><a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m.html" title="A simple ROM implementation which supports simulation and synthesizable HDL generation. ">ROM</a> size (i.e. number of words)  <a href="#a614f68bf16763fbfa0fa91d5c9c9e228">More...</a><br/></td></tr>
<tr class="separator:a614f68bf16763fbfa0fa91d5c9c9e228 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memSeparator" colspan="2">&#160;</td></tr>
<tr class="memitem:a4872aa7106d668871f38adb20bd05290 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memItemLeft" align="right" valign="top">uint&#160;</td><td class="memItemRight" valign="bottom"><a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html#a4872aa7106d668871f38adb20bd05290">Width</a><code> [get]</code></td></tr>
<tr class="memdesc:a4872aa7106d668871f38adb20bd05290 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="mdescLeft">&#160;</td><td class="mdescRight">Width of data word  <a href="#a4872aa7106d668871f38adb20bd05290">More...</a><br/></td></tr>
<tr class="separator:a4872aa7106d668871f38adb20bd05290 inherit properties_interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m"><td class="memSeparator" colspan="2">&#160;</td></tr>
</table>
<a name="details" id="details"></a><h2 class="groupheader">Detailed Description</h2>
<div class="textblock">
<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00074">74</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>
</div><h2 class="groupheader">Member Function Documentation</h2>
<a class="anchor" id="aedf8ae4d903829f56bee37cf54c055fe"></a>
<div class="memitem">
<div class="memproto">
      <table class="memname">
        <tr>
          <td class="memname">void SystemSharp.Components.Std.ROMContractClass.PreWrite </td>
          <td>(</td>
          <td class="paramtype"><a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a>&#160;</td>
          <td class="paramname"><em>addr</em>, </td>
        </tr>
        <tr>
          <td class="paramkey"></td>
          <td></td>
          <td class="paramtype"><a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a>&#160;</td>
          <td class="paramname"><em>data</em>&#160;</td>
        </tr>
        <tr>
          <td></td>
          <td>)</td>
          <td></td><td></td>
        </tr>
      </table>
</div><div class="memdoc">

<p>Pre-initializes the <a class="el" href="class_system_sharp_1_1_components_1_1_std_1_1_r_o_m.html" title="A simple ROM implementation which supports simulation and synthesizable HDL generation. ">ROM</a> with word <em>data</em>  at address <em>addr</em> . Called during elaboration, never at model runtime. </p>

<p>Implements <a class="el" href="interface_system_sharp_1_1_components_1_1_std_1_1_i_r_o_m.html#a583ad67b555f55d9768aa104f055d321">SystemSharp.Components.Std.IROM</a>.</p>

<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00117">117</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>

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<h2 class="groupheader">Property Documentation</h2>
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<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00083">83</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>

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<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00077">77</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>

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          <td class="memname"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328ea7c147cda9e49590f6abe83d118b7353b">Out</a>&lt;<a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic_vector.html">StdLogicVector</a>&gt; SystemSharp.Components.Std.ROMContractClass.DataOut</td>
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<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00098">98</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>

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          <td class="memname">uint SystemSharp.Components.Std.ROMContractClass.Depth</td>
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<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00108">108</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>

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          <td class="memname"><a class="el" href="namespace_system_sharp_1_1_components.html#a1b363c1bde8fdda4245b1c5c616e328eaefeb369cccbd560588a756610865664c">In</a>&lt;<a class="el" href="struct_system_sharp_1_1_data_types_1_1_std_logic.html">StdLogic</a>&gt; SystemSharp.Components.Std.ROMContractClass.RdEn</td>
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<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00092">92</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>

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          <td class="memname">uint SystemSharp.Components.Std.ROMContractClass.Width</td>
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<p>Definition at line <a class="el" href="_block_mem_8cs_source.html#l00113">113</a> of file <a class="el" href="_block_mem_8cs_source.html">BlockMem.cs</a>.</p>

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<hr/>The documentation for this class was generated from the following file:<ul>
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